- Bit 7: cfINPUT
This bit is read-only. Any attempt to set or clear this bit is ignored. This bit indicates whether the channel is in a state that will accept input or not (either from the host or from the PWM inputs). It is cleared in order to protect the current output signal from being disturbed. Therefore, it is used as part of the Fail-Safe mechanism to control signal processing. It is disabled when Fail-Safe is active and the channel is configured for R/C Fixed mode operation.
When the channel is in R/C Fixed mode, this means that the channel is supposed to keep the output signal fixed to match the last good input signal that was received. This mode persists whether Fail-Safe operation is enabled for the channel or not, making it somewhat of an exception. While Fail-Safe is engaged, cfINPUT is disabled to prevent any signal, deliberate or otherwise, from affecting the output signal. When Fail-Safe disengages, cfINPUT is enabled and the channel will once again be responsive to changes in the input signal.
Reading this bit helps determine the current state of the respective channel. The default state of this bit depends on the pre-defined configuration that is loaded from EEPROM during power-on reset. The factory default settings cause this bit to be set on power-up, enabling the channel input. The cfINPUT bits from each of the four channels are also mapped into a single byte that is returned by the Read RC4 Status command or from Extended Data Level 2 of the Read Channel Data command, and are referred to as the Bit-Mapped Channel Input Enable Bits.
cfINPUT, like cfPASSTHRU, affects sampling. When cfPASSTHRU=1, sampling is disabled. Sampling is also disabled when cfINPUT=0. However, unlike cfPASSTHRU, when cfINPUT=0 the input signal is not passed along to the output (in other words, there is no pass-thru). Instead, the input signal is completely ignored. In fact, cfINPUT takes precedence over cfPASSTHRU. When cfINPUT=0, this is equivalent to physically unplugging the channel input source.
- Bit 6: cfOUTPUT
This read/write bit is used to turn the channel output on or off. If the output is used to drive a servo, then turning the output off can be useful as a power-saving measure. The default state of this bit depends on the pre-defined configuration that is loaded from EEPROM during power-on reset. The factory default settings cause this bit to be set on power-up, enabling the channel output.
The state of cfOUTPUT affects all modes and is straight-forward. Either an output is on or it is off. When it is off, the channel output pin is driven low. Note, however, that the output signal generation timing remains unchanged whether the output is enabled or disabled. For example, if the output is turned off for channel 2, there simply will be no pulse on channel 2 for the period of time when there normally would be a pulse. For instance, if an output pulse on channel 2 is 1.5ms long, there will be a 1.5ms gap between the output pulses of channel 1 and channel 3.
- Bit 5: cfSIGNAL
This bit is read-only. Any attempt to set or clear this bit is ignored. This bit indicates if a valid signal was detected on the channel input. This operates independently of cfINPUT. Whether or not cfINPUT is enabled, cfSIGNAL can still report the presence of a valid signal on the channel input. However, if the input is configured as physically disconnected via the Physical Input Connections command (whether it is physically disconnected or not), cfSIGNAL will not report the presence of any valid signal, even if one is present.
- Bit 4: cfINITWAIT
This read/write bit, when set, prevents any signal from being generated on the output (regardless of the setting of any other mode bit) until Fail-Safe has been disengaged at least once since power-up. This is useful in applications where a solid PWM (R/C) input signal must be present before any control signals are delivered to the output.
This bit applies equally to a channel operating in either Command mode or R/C mode. If set on all channels, it is useful for bringing all outputs online simultaneously when Fail-Safe is disengaged.
NOTE: If RC4 is configured to power-up in the online state (i.e. with Fail-Safe disengaged), this will defeat the usefulness of cfINITWAIT as all channels outputs will become active immediately on power-up.
Also be aware that a channel configured to power up on R/C Fixed mode (see below) will behave as if cfINITWAIT is set (regardless of its setting) if no signal is present when RC4 is powered up.
- Bit 3: cfPASSTHRU
This read/write bit effectively controls whether an input signal is sampled or not. Normally, a signal appearing on a channel input is sampled so that a pulse width measurement is available for reading (via the Read Channel Data command), and the signal is also replicated on the channel output. If cfPASSTHRU is set, this essentially turns off input sampling, which means a current pulse width value is not available (stale data will be read, instead). However, the signal is still replicated on the output.
cfPASSTHRU applies to channels in all operating modes. Even when a channel is configured for a Command mode, any signal appearing on the channel input is still sampled and its value is obtainable through Read Channel Data. The setting of cfPASSTHRU does not affect the behavior of a channel, regardless of what mode it is in. The only difference is that current sampled signal values are not available. Setting cfPASSTHRU, in effect, freezes a snapshop of a channel input pulse width value at a particular point in time.
Note that cfPASSTHRU only applies to channel input signals (pulse width values). It does not lock in status information. The channel continues to behave as expected, and status can and will change according to current signal activity. Therefore, when reading status information for a channel with cfPASSTHRU set, keep in mind that the status information will not be in synch with the sampled signal values, because they reflect two different points in time.
Also be aware that cfPASSTHRU applies to input sampling, only. If RC4 is configured to report pulse width values from the outputs instead of the inputs (see the mfIOTABLE bit in the RC4 Mode command), the setting of cfPASSTHRU will not affect the readings as output signal samples are always current.
Clearing the cfPASSTHRU bit will restore normal input sampling functionality immediately.
- Bits 2-0: cfMODE
These three read/write bits are used to specify the mode of operation for a channel.
There are basically two distinct modes of operation, R/C mode and Command mode, each of which is broken down into four variations, providing a total of eight possible operating modes in which a channel can operate. Only one mode of operation can be selected at any given time for a channel, although each channel can be set to a different mode, independently.
Generally, when a channel operates in R/C mode, the signals applied to the channel input are sampled and reproduced on the channel output. When a channel operates in a Command mode, channel input signals are still sampled, but they are not reproduced on the output. Instead, commands must be issued to RC4 to tell the output what signal to generate.
In either R/C or Command mode operation, any signal appearing on a channel input is sampled and available to read via the Read Channel Data command.
The following table lists the eight possible modes of operation:
See the behavior table, below, for more detailed information about how a channel behaves in each of these modes.cfMODE Mode 000 R/C 001 R/C Fixed 010 R/C Fail-Safe 011 R/C Presets 100 Command 101 Command Override 110 Command Fail-Safe 111 Command Protected
Note: If a channel is configured to power-up in R/C Fixed mode, this creates a situation where the channel has no input signal data to pass along to the output if no input signal is present at power-up. In this case, the output will be driven low (i.e. no signal will be generated) until a good signal is present long enough to disengage Fail-Safe. This is effectively the same behavior as seen with the cfINITWAIT bit (see above).
RC4 Servo Monitor & Controller
(Revision F)
NOTICE: This document is a work-in-progress.
Last Updated:
January 3, 2007
For questions or comments about RC4, please write to rc4@codesmart.com.Table of Contents
- 1. Introduction
- 2. Programming
- 2.1 RC4 Serial Interface Commands
- 2.2 RC4 Normal Commands
- 2.3 RC4 Special Commands
- 2.4 RoboBRiX Interrupt Commands
- 2.5 RoboBRiX Shared Commands
- 3. Hardware
- 4. Firmware
- 5. Software
- 6. Issues
- 7. Documentation
1. Introduction
RC4 can sample up to five PWM inputs and control up to four
PWM outputs, independently or simultaneously. Various operating parameters can
be specified for the module, and various modes of operation can be specified on
a per-channel basis. The fifth input (referred to as "Channel 5") is one of six
signal sources that can be used for pulse-width controlled event triggering and
is provided as a dedicated input for event triggering.
The Revision F prototype is seen here on its test bed with a Futaba 7-channel
receiver (with five channels connected to the inputs) and four standard R/C servos
connected to the outputs. This board represents a significant size reduction compared
to the Revision A board (see below). There is currently no RC4 board designed to
conform to RoboBRiX dimensions, but there may be one on the horizon.
1.1 Features
One primary feature of RC4 is its Fail-Safe mode. This feature provides the core
functionality for switching between host control and radio control (R/C) in response
to loss of input signal, which is the fundamental reason RC4 was initially created.
Fail-safe is an integral part of RC4 and cannot be disabled. However, each channel can
be configured independently to ignore Fail-Safe or to respond to it in various ways.
RC4 uses an elegant, yet extremely reliable algorithm for analyzing signal quality
to determine when to activate and deactivate Fail-Safe mode, even in environments where a
radio signal is susceptible to interference or drop-out. Fail-Safe mode also can be deliberately
activated either by issuing a command over the serial port, or by assigning "Fail-Safe On Demand"
control to the Trigger Input.
The Trigger Input can be driven by one of two possible input sources, selectable via a jumper
block on the board. Typically, the Channel 5 input is used to drive the Trigger Input, although
the channel 1 input is an alternative selection. Currently, the only built-in triggering
feature is to enable Fail-Safe on demand. However, a host processor can monitor the Trigger
Input via the serial interface and provide its own triggering functions as needed in a custom
application.
When RC4 is powered up, it comes up with Fail-Safe engaged, by default. If signal is present, Fail-Safe
will disengage after RC4 determines a good signal is being received. This signal detection delay is
approximately one second long. Once Fail-Safe is disengaged, it will re-engage after input signal
is absent for approximately one second. Advanced users can modify these delays to some extent,
although it is not recommended unless absolutely necessary.
Each of the four main channels can be configured for various modes of operation. How a
channel behaves in Fail-Safe mode is determined by settings that are encoded within its
Channel Configuration Byte.
The mode of a channel is configured by setting or clearing bits within this byte and writing the byte
to RC4 through the Write Channel Configuration command.
Four configuration bytes are
required for a complete configuration; one for each of the four channels.
For more complete, detailed information about each of the modes in which a channel
can operate, refer to the Channel Behavior Table in the
Channel Configuration Byte section.
Channel 5 is a special input channel (with no corresponding output) that can be selected as the Trigger
Input for various triggering events. Trigger events can be enabled or disabled via the
Trigger Enable command. Event triggering is based on the pulse width of the
input signal applied to the Trigger Input. Currently, there is only one trigger point, or threshold,
that determines when events are to be triggered, and the only built-in trigger event
available in RC4 is to force the activation of Fail-Safe, on demand.
This feature is better known as Fail-Safe-on-Demand (or FSOD). FSOD can either be assigned
to the Trigger Input, or it can be controlled through the RC4 Mode command.
These two methods of controlling FSOD are exclusive. If the control is enabled on the Trigger Input, then
it cannot be requested via the RC4 Mode command and visa versa.
Regardless of the events enabled on the Trigger Input, the pulse width of the signal applied to the
Trigger Input can be retrieved at any time through the Read Trigger Input
command. This enables a host controller to establish its own triggering options
based on values read from RC4. Note that the Trigger Input does not impose any pulse width restrictions
(other than a 16-bit pulse width measurement limitation), so all signals good and bad are equally
sampled. However, whenever the Trigger Input is selected as the FSOD trigger and no input signal is present, the
Read Trigger Input command will return zero. Normally, the Read
Trigger Input returns the value of the last signal sampled (no matter how long ago it was detected) under
all other conditions.
1.2 Fail-Safe Operation
Fail-Safe is an integrated function of RC4 that cannot be disabled. However, as noted in the
Features section, above, a channel does not have to observe or respond to
Fail-Safe.
Fail-Safe is really just a state within RC4 that can be either on (activated, or engaged) or off
(deactivated, or disengaged). Channels can be configured to respond to changes in the Fail-Safe
state or to ignore the Fail-Safe state all together.
Although channel behavior can be configured to ignore Fail-Safe, the control of Fail-Safe activation
and deactivation depends on signals applied to the channel inputs. Fail-Safe does not descriminate
between inputs (except when Noise Rejection is enabled - more on that later). If a valid signal appears
on one or more inputs - regardless of whether the respective channel is configured to observe
Fail-Safe or not - Fail-Safe will disengage once it determines the signal has been present and valid
for a certain period of time (typically one second, approximately). Similarly, if there is no valid
signal present for a certain period of time, Fail-Safe will engage.
It is important to know that the Fail-Safe state applies to RC4 as a whole (i.e. it is not a
per-channel state) and that a signal on only one channel is required to deactivate Fail-Safe,
which could affect the remaining channels, depending on their individual configurations.
Note that Fail-Safe engagement/disengagement is based upon only those inputs that are defined to have
a physical connection (see the Physical Input Connections command).
If RC4 is defined to have no inputs physically connected, then this creates a situation where Fail-Safe
can never be disengaged. In the presence of signals, with physical input connections defined, Fail-Safe
can be forcibly activated through the mfFAILSAFE and mfFSODNOW bits of the RC4 Mode
command, but there is no way to forcibly disengage Fail-Safe. The only way Fail-Safe can
be disengaged is through detection of a valid input signal on one of the physical input connections.
There are a number of aspects that define what RC4 considers to be a valid signal. The most fundamental
aspect is the pulse width. The pulse width of an incoming signal must be within the MIN and MAX
pulse width values that are pre-determined either through the PWM Input
Configuration command, or defined explicitly through the Write PWM
Configuration command.
Another factor in determining when to activate or deactivate Fail-Safe involves signal continuity.
Especially in R/C applications, there can be moments of temporary signal loss. If Fail-Safe were
to engage every time an expected input signal did not arrive, RC4 would likely cause its intended
application to become unstable, with Fail-Safe spontaneously engaging unexpectedly. Therefore, there
are some parameters that allow for momentary gaps in the input signal. This is true when RC4 is
in the process of determining when to deactivate Fail-Safe as well as during the process of determining
when to activate Fail-Safe.
The Write Fail-Safe Operating Parameters command is provided
for advanced RC4 users to specify the parameters that are used by RC4 to descern signal quality. These
parameters determine the length of time a signal must be present or absent for RC4 to deem the signal
good or bad before altering the Fail-Safe state. They also determine how much of a gap is allowed in
a signal to consider its presence valid when determining whether to engage Fail-Safe, or how many
consecutive pulses must arrive in order for a signal to be considered when determining whether to
disengage Fail-Safe.
It is unwise to indiscriminately alter these values without understanding how they affect Fail-Safe
activation and deactivation, but it is safe to experiment under controlled conditions as long as the
settings are not saved to EEPROM until their desired effect has been achieved. The integrity of RC4
can become impaired if these settings are not altered correctly.
RC4 offers an enhanced Fail-Safe mode of operation when Noise Rejection is enabled. When Noise
Rejection is enabled, all inputs that have been
defined as having a physical connection to RC4 must have a valid signal present in order for Fail-Safe
to disengage. Also, any and all channels that are configured to recognize changes in Fail-Safe
status (R/C Fixed, R/C Fail-Safe, R/C Presets and Command Protected modes)
will respond immediately to signal gaps by locking in the last good signal
received (for R/C modes) or by switching back to host control (for Command modes). After a short
delay, if signal continuity remains valid, control will resume. This is a
sort of preliminary Fail-Safe measure that locks in good signals in the event of sudden signal loss
while also blocking out any intermittent or "noisy" signals (that may otherwise be considered valid),
up until the time when either Fail-Safe engages, or the signal quality returns to normal.
2. Programming
RC4 provides a command interface via the serial port to allow a host to access and control the data
and functions available within. The serial port can operate at one of eight selectable speeds,
ranging from 1200bps to 57600bps. The factory default setting is 2400bps, for compatibility
with RoboBRiX. This, as well as many other operating parameters, can be changed and saved in
the internal EEPROM so that power-on defaults can conform to your application.
Commands issued to RC4 consist of one or more bytes and may result in one or more bytes of data
returned in response. If a command returns more than one byte of data, this data may be returned
in a continuous stream, or one byte at a time, depending on an RC4 Interface Configuration
setting. One debug
command (not available in the released firmware) consistently delivered 176 bytes of data at
57600bps without a hitch. The serial interface operates in full-duplex mode at all times
(which means it can send and receive data at the same time). Although it is not absolutely necessary,
it is good practice to wait for results from one command before issuing the next, and to add time delays
between successive commands that return no data, for it is possible to overrun the internal command
buffers or to miss data if RC4 is driven too hard too fast.
RC4 also provides a means of defining the byte order (or "Endianness") of data read from or written
to the device. Some hosts (such as PCs) operate in "Little Endian" mode, which means the lower-value
byte is sent and stored first, followed by the higher-value byte, of a two-byte value. Other host
processors may operate in "Big Endian" mode, which means the higher-value byte is sent and stored
first, followed by the lower-value byte. Some data exchanged between RC4 and the host are two-byte
(word) values - especially pulse-width signal data - so these values are delivered in the byte order
as specified by the Endianness setting. The factory default setting is Little Endian mode. This
setting can be changed and saved in the internal EEPROM to conform to your system specifications.
2.1 RC4 Serial Interface Commands
The following table lists the entire serial interface command set for RC4. All command codes are
listed in hexadecimal. It is important to remember this, as all references to
command codes in this document are presented in hexadecimal (whether explicitly indicated or not).
In the grouping referred to as "RC4 Normal Commands", command codes 00 through 09
are arranged such that all even-numbered command codes (bit 0 = 0) are read operations, and
odd-numbered command codes (bit 0 = 1) are write operations.
Command codes between 0A and 0F are free-form and currently consist of reads for which there is no
direct corresponding write command. Many of the values read from this group of commands can be
specified through the RC4 Special Commands. RC4 Special Commands
either invoke seldom-used, special functions (like saving settings
to EEPROM), or define RC4 configuration settings.
All RoboBRiX commands are described in the
RoboBRiX Specifications
document. RoboBRiX interrupts are currently not implemented in RC4, nor are the clock-related
commands.
2.2 RC4 Normal Commands
2.2.1 Read Channel Data (0x00)
The Read Channel Data command returns one of four data sets, depending on the Extended Data Level
specified in the RC4 Interface Configuration command. Note
that the extended data level is cumulative. For example, extended data level 3 includes
the base information, plus the data from level 1, plus the data from level 2, as well as
the additional data for level 3. Data is delivered in the order in which is it presented in the
table, below.
The table below lists the data values that are returned from the Read Channel Data command,
and the number of bytes of data for each value.
00: Read Channel Data Base Data Bytes Channel 1 pulse width
Channel 2 pulse width
Channel 3 pulse width
Channel 4 pulse width2
2
2
2Extended Data Level 1 adds: Trigger Input pulse width 2 Extended Data Level 2 adds: Bit-mapped Channel input enable bits
Bit-mapped Channel input detection bits
RC4 Status Flags Byte #1
RC4 Status Flags Byte #2
1
1
1
1Extended Data Level 3 adds: RC4 Error Code
RC4 Mode Settings1
1
The pulse width values returned for Channels 1 through 4 are sampled either from the PWM
inputs, or from the outputs, depending on the mfIOTABLE bit setting specified in the
RC4 Mode command. The byte order of each of the two-byte values is
determined by the Endianness setting specified in the RC4
Interface Configuration command. These pulse width values are 13-bit values that represent 1/3us
increments. Therefore, to translate a pulse width value into microseconds, simply divide the
pulse width value by 3.
Note that if a channel is configured for "Pass-Thru" operation (see the
Channel Configuration Byte),
then its pulse width value will be the value of the signal that was sampled last just before cfPASSTHRU
mode was enabled for the channel. If the channel is configured to power up in cfPASSTHRU mode, then the
data returned will represent signal presets stored in the internal EEPROM either from the factory or
from the most recent execution of the RC4 Special Function command
(to save current channel values to Fail-Safe EEPROM).
2.2.2 Write Channel Data (0x01)
| 01: Write Channel Data | |
|---|---|
| Value | Bytes |
| Channel 1 pulse width Channel 2 pulse width Channel 3 pulse width Channel 4 pulse width |
2 2 2 |
The Write Channel Data command is used to provide output signal values to channels 1 through 4.
A value written to a channel through this command is applied to the channel output only if the
channel is configured for one of the Command modes or for
R/C Fail-Safe mode with Fail-Safe engaged (see the
channel behavior table within the
Write Channel Configuration command detail).
It is important to remember that values written to the channel outputs remain unchanged until new
values are written. If a channel switches between R/C and host control, the channel output will
revert to the last signal written whenever it switches to host control. If a channel is in Command
mode at the time a new value is written, the output will respond immediately. Also note that all
channel output values are updated at once following the Write Channel Data command, and only after
an output cycle completes. In other words, if RC4 is currently generating output signals based on
previous data when new data is written, the new values take effect only after the current output
cycle completes. This ensures that all outputs change in unison (i.e. predictably).
Data written via the Write Channel Data command may be saved to EEPROM.
An RC4 Mode bit (mfIOEEPROM) is used to select what
signal data gets saved to EEPROM when an RC4 Special Function
command is issued to save channel presets. If mfIOEEPROM is set, then channel data that was last
written via Write Channel Data will get saved to EEPROM when the save operation is executed. These
saved presets subsequently can be used by channels that are configured for the
R/C Presets mode of operation when Fail-Safe is engaged.
Note that the channel pulse width values represent 1/3us increments. Therefore, to compute the
pulse width value for a desired pulse width in microseconds, simply multiply the desired pulse width
by 3. For example, for a 1500us pulse, a value of 4500 (or 1194 in Hexadecimal) must be written.
2.2.3 Read Channel Configuration Options (0x02)
| 02: Read Channel Configuration | |
|---|---|
| Value | Bytes |
| Channel 1 Configuration Channel 2 Configuration Channel 3 Configuration Channel 4 Configuration |
1 1 1 |
This command reads the channel configuration bytes for each of the four base channels.
See the Write Channel Configuration command, below, for detailed
information regarding the format of these bytes.
2.2.4 Write Channel Configuration Options (0x03)
| 03: Write Channel Configuration | |
|---|---|
| Value | Bytes |
| Channel 1 Configuration Channel 2 Configuration Channel 3 Configuration Channel 4 Configuration |
1 1 1 |
The Channel Configuration Byte
Each of the four channels can be configured for various modes of operation. How a
channel behaves in Fail-Safe mode is determined by the mode settings that are encoded
in its Channel Configuration Byte.
The mode of a channel is configured by setting or clearing bits within this byte, which is
written to RC4 through the Write Channel Configuration command. This command requires four
channel configuration bytes for a complete configuration, one for each channel.
Note that this command affects all four channels in unison. The channel configuration settings are
applied to all channels simultaneously, so there is no sequencing issues to be concerned with. Also,
if RC4 is in the middle of sampling input signals or generating output signals when this command is
issued, the new settings will not take effect until the beginning of the following input cycle.
Channel Configuration Byte Bit Assignments 7 6 5 4 3 2 1 0 cfINPUT cfOUTPUT cfSIGNAL cfINITWAIT cfPASSTHRU cfMODE
Channel Behavior Table
The available modes of operation provide a versatile array of behavior patterns
that can be creatively applied to many applications.
The table below lists the channel configuration modes that RC4 currently provides. It lists
the official name for each of the modes, and describes the behavior of each mode when Fail-Safe is
engaged or disengaged. Keep in mind that the different modes exist primarily to define how a channel
responds to changes in the Fail-Safe state. Therefore, certain states will exhibit the same
behavior as other states. In fact, there are only five unique states, or behaviors. Each unique
behavior is color-coded in the table for easy identification.
This table does not include the cfINPUT, cfOUTPUT, cfPASSTHRU or cfINITWAIT flags, as their
effective behavior is independent of the selected operating mode.
Channel Configuration Byte -- Per Channel Mode Name Behavior when... Fail-Safe is Disengaged (Good Signal) Fail-Safe is Engaged (Signal Bad or Absent) R/C Output responds to input, when present. Output is held at last good signal when signal is absent. Output responds to input, when present. Output is held at last good signal when signal is absent. R/C Fixed Output responds to input, when present. Output is held at last good signal when signal is absent. Output is held at last good signal received before Fail-Safe engaged. Input signal ignored. R/C Fail-Safe Output responds to input, when present. Output is held at last good signal when signal is absent. Output responds to host. Input signal ignored. R/C Presets Output responds to input, when present. Output is held at last good signal when signal is absent. Output reverts to preset values retrieved from EEPROM. Command Output responds to host. Input signal ignored. Output responds to host. Input signal ignored. Command Override Output responds to host if no input signal is present. Output responds to input immediately upon reception of input signal. Output responds to host if no input signal is present. Output responds to input immediately upon reception of input signal. Command Fail-Safe Output responds to host. Input signal ignored. Output responds to host. Input signal ignored. Command Protected Output responds to host if no input signal is present. Output responds to input immediately upon reception of input signal. Output responds to host. Input signal ignored.
NOTE: The behavior for a channel that responds to input signals is further modified if the Noise
Rejection option is enabled. The behaviors listed here do not include Noise Rejection.
The following table presents a more detailed explanation of each of the operating modes:
Mode Description R/C This mode is used for a channel that needs to respond exclusively to the PWM inputs (typically for R/C use). Fail-Safe mode is ignored. This means there is no change in how the channel behaves when Fail-Safe is engaged. However, a channel in this mode will exhibit a sort of mock fail-safe behavior, as the signal at the channel output will always reflect the last good input signal received, even after input signal is lost. Keep in mind, however, that if an input signal arrives due to interference or "noise" and the signal falls within valid parameters, this signal will immediately become the new output signal. Therefore, this mode is potentially susceptible to inadvertent changes. R/C Fixed This mode is a step up from straight R/C mode. The behavior of a channel configured in this mode is the same as a channel in R/C mode, except that this mode responds to Fail-Safe and is far less susceptible to inadvertent signal changes due to "noise". If input signal is lost, the output signal reflects the last good input signal, just as in R/C mode. It is also susceptible to changes until Fail-Safe engages, but as soon as Fail-Safe engages, the output signal is locked in. The output signal cannot and will not change as a result of a new input signal until Fail-Safe disengages. R/C Fail-Safe A channel configured in this mode responds to changes in Fail-Safe status by switching between R/C (PWM) input control to Command (or "host") control. When RC4 product development began, this was the only mode defined in the specs. In other words, this was the reason RC4 was created. This mode enables an application to switch between radio control (assuming the inputs are connected to an R/C receiver) and autonomous control (to respond to commands from the serial interface). When input signal is present, the channel output in this mode responds to the input signal just as it does in R/C mode. As soon as signal is lost, the last good input signal is held on the output. However, as soon as Fail-Safe engages, the output signal immediately changes to reflect the last pulse width value that was written to RC4 via the Write Channel Data command from the host. As long as Fail-Safe is engaged, the channel output will respond to updates from the host. As soon as Fail-Safe disengages (after detecting a good input signal), the output once again responds to the PWM input signals.
R/C Fail-Safe mode is similar to Command Override and Command Protected modes (see below) but with subtle, yet significant, distinctions.R/C Presets A channel configured in this mode responds to input signals and changes in Fail-Safe status in the same way as the other R/C modes, except when Fail-Safe engages, the output is fixed at a pre-determined signal value instead of switching to host control. Host control is ignored, entirely, in this mode. This pre-determined signal value comes from values stored in the internal EEPROM either from the factory or from a previous RC4 Special Function command issued via the serial interface from the host. Command A channel configured for Command mode responds exclusively to the host (via the Write Channel Data command). Fail-Safe is ignored in this mode. This means that the behavior of the channel does not change in respect to changes in Fail-Safe status. In this mode, a channel basically behaves how one might expect a channel from any standard serial servo controller to behave. Command Override In the Command Override mode, the output of a channel remains under host control in its natural state. However, any valid signal appearing on the input will immediately override host control - even if only for a beat. This mode is actually similar in behavior to R/C Fail-Safe mode, except for two distinct differences: 1) Command Override mode does not respond to changes in Fail-Safe status, and 2) switching between host control and R/C control is instantaneous, based on the presence or absence of any valid input signal (irrespective of Fail-Safe status). This means that, at all times, a channel in Command Override mode will respond, immediately, to any valid input signal, and will revert back to host control immediately upon removal of valid input signal. This mode is useful for applications that operate in an autonomous capacity, but need to respond immediately to radio control (or other external signal source connected to the inputs), such as a mobile robot, for example.
Camp Peavy's Springy Thingy from the Home Brew Robotics Club comes to mind as an ideal prospect.Command
Fail-SafeCurrently, a channel in the Command Fail-Safe mode behaves identically to a channel in Command mode. This is simply because Command Fail-Safe mode has the same behavior associated with both Fail-Safe states. In other words, technically, internally, this mode recognizes changes in Fail-Safe status, but no change in behavior has been defined.
An alternative behavior may be defined in a future version of RC4. Therefore, it is recommended to use Command mode, instead.Command Protected This mode is sort of a cross between Command Override mode and R/C Fail-Safe mode, and its behavior is dependent on Fail-Safe status. If Fail-Safe is engaged (i.e. no input signal is present), then the channel remains under host control - just as in R/C Fail-Safe mode. And, unlike Command Override mode, where any input signal will immediately override the host, the output will only respond to the input once Fail-Safe has disengaged. In this respect, the transition from host control to R/C control is the same as in R/C Fail-Safe mode. However, if Fail-Safe is disengaged and the input signal goes away, the channel behaves like Command Override mode in that host control takes over immediately. If signal is regained before Fail-Safe engages, the output will again respond, immediately, to the input signal. However, if Fail-Safe engages before input signal is regained, output will remain in host control once again until Fail-Safe disengages, before responding to input signals again. The net effect of this mode is that the host takes control whenever signal is lost - even if only for a beat - and the host control is protected from spurious input signals when Fail-Safe is engaged.
R/C Fail-Safe is the best mode for the most stable transition between R/C and host
control, since Fail-Safe will not disengage until a solid R/C signal is present, and host control
will not resume until Fail-Safe engages after a solid loss of signal. Engaging Fail-Safe through
the Fail-Safe-on-Demand (FSOD) feature provides an additional level of reliability,
because all PWM inputs (except the "Trigger Input") are ignored in this state.
2.2.5 Read PWM Signal Configuration (0x04)
| 04: Read PWM Configuration | |
|---|---|
| Value | Bytes |
| Minimum Pulse Width Maximum Pulse Width |
2 |
The Read PWM Signal Configuration command returns the current minimum and maximum pulse width
values that are used by RC4 to determine whether an input signal is valid or not. A pulse width received
on any channel input must be within these limits (inclusive) to be considered valid. Any signal pulse
that is shorter than the minimum or longer than the maximum is rejected.
The minimum and maximum pulse width values apply to all channels equally -- there is currently no way
to specify a valid signal range for each individual channel. These values defined by the
Write PWM Signal Configuration command. The
PWM Input Configuration command may affect these values as well
(particularly the maximum pulse width value).
2.2.6 Write PWM Signal Configuration (0x05)
| 05: Write PWM Configuration | |
|---|---|
| Value | Bytes |
| Minimum Pulse Width Maximum Pulse Width |
2 |
The Write PWM Signal Configuration command is used to establish a range, or "window",
within which a pulse width arriving on any channel input must fall to be considered valid. A signal
having a pulse width that is shorter than the minimum or longer than the maximum will be rejected.
The pulse width value for a rejected signal is not available for reading, and no attempt is made to
reproduce the signal on the respective channel output.
Write PWM Signal Configuration is typically performed following a
PWM Input Configuration command in order to adjust the minimum and
maximum values to something that is more meaningful to the application.
The PWM Input Configuration command establishes absolute
minimum and maximum values, based on the characteristics defined for the specified index.
The Write PWM Signal Configuration command can then be used to modify
the settings for a narrower pulse width window. However, the range cannot be extended wider than
the absolute limits imposed by the PWM Input Configuration command. Any attempt to set
minimum or maximum values beyond their absolute limits will result in the respective value being
set equal to its absolute limit. The Read PWM Signal Configuration
command can be used at any time to determine what the actual settings currently are. Once set,
the settings remain unchanged until a subsequent command is issued to change them.
Note that if the minimum value is set larger than the maximum value, then all signals will be rejected.
Also, if the input signals for a particular application never fall within the specified pulse width
range, then they, too, will be rejected. If all signals are rejected for a period of time equal to
that specified for Fail-Safe to engage, then Fail-Safe will engage (see
Write Fail-Safe Parameters).
2.2.7 Read Fail-Safe Operating Parameters (0x06)
NOTE: All values are in hexadecimal:| 06: Read Fail-Safe Parameters | ||
|---|---|---|
| Value | Bytes | Default |
| Cycles to Engagement Cycles to Disengagement Signal Continuity Cycles Signal Gap Cycles |
1 1 1 |
37 20 5 |
The Read Fail-Safe Operating Parameters command returns values that are used in the
activation and deactivation of the internal Fail-Safe mechanism. These values determine how
the input signals are analyzed in order for RC4 to decide when to activate or deactivate
Fail-Safe. These values can be changed using the
Write Fail-Safe Operating Parameters command. However,
this practice is discouraged without full knowledge of how the Fail-Safe mechanism works,
since incorrect settings can cause RC4 to malfunction or stop working completely.
For more detailed information regarding the meaning of these values, refer to the
Write Fail-Safe Operating Parameters command.
2.2.8 Write Fail-Safe Operating Parameters (0x07)
| 07: Write Fail-Safe Parameters | |
|---|---|
| Value | Bytes |
| Cycles to Engagement Cycles to Disengagement Signal Continuity Cycles Signal Gap Cycles |
1 1 1 |
The Write Fail-Safe Operating Parameters command specifies values that are used in the
activation and deactivation of the internal Fail-Safe mechanism. These values determine how
the input signals are analyzed in order for RC4 to decide when to activate or deactivate
Fail-Safe.
WARNING: The use of this command is discouraged without full knowledge of how
the Fail-Safe mechanism works, since incorrect settings can cause RC4 to malfunction or stop
working completely!
- Cycles to Engagement
This value has meaning only when Fail-Safe is disengaged.
This 8-bit value specifies how many input cycles must elapse with no valid signal present before Fail-Safe is engaged. The factory default value is 0x35 (53 in decimal) which, for an 18ms frame rate selection, results in a delay time of approximately one second. Due to the way the signal cycles and timeouts are implemented in RC4, when no signal is present and an 18ms frame rate is selected, a signal cycle actually takes 19ms. Therefore, 53 consecutive signal cycles with no valid signal present works out to be 53x19ms = 1007ms (or 1.007 seconds). This time will vary slightly depending on frame rate selection (maximum approaching 1.2 seconds). - Cycles to Disengagement
This value has meaning only when Fail-Safe is engaged.
This 8-bit value specifies how many input cycles must elapse with valid signal present before Fail-Safe is disengaged. The factory default value is 0x37 (55 in decimal) which, for an 18ms frame rate selection, results in a delay time of approximately one second. When signal is present for a signal that has an 18ms frame rate, the actual signal cycle is 18ms (i.e. the same as the frame rate of the actual signal). Therefore, 55 consecutive signal cycles with valid signal present works out to be 55x18ms = 990ms (or 0.99 seconds). This time will vary slightly depending on frame rate selection (maximum approaching 1.2 seconds). - Signal Continuity Cycles
This value has meaning only when Fail-Safe is disengaged.
During normal operation, there may come a situation where the input signal is removed (for example, when an R/C transmitter is shut off). In an environment where RF transmission is used (such as in R/C), it is possible that the receiver could pick up spurious noise when there is no valid signal being transmitted. This signal, when fed into RC4, might otherwise be interpreted as valid signals (from the perspective of the Fail-Safe mechanism) and cause the Fail-Safe engagement timeout to reset, preventing Fail-Safe from engaging.
Likewise, if a solid input signal becomes weak or disrupted and one or two input cycles are lost, it would be undesirable to engage Fail-Safe solely as a result of this brief signal loss.
The Signal Continuity Cycles value specifies how many valid signals must be detected between the time signal is lost and the time Fail-Safe engages in order for the signal to continue to be considered valid. This actually serves two purposes - the first is to reduce the possibility that Fail-Safe will not engage due to noise, and the second it to reduce the possibility that Fail-Safe will engage if an incoming signal is weak or lost only temporarily.
The factory default value for Signal Continuity Cycles is 0x20 (or 32 in decimal); therfore, 32 input cycles with valid signal present, out of 53 cycles (specified by Cycles to Engagement) must occur to maintain Fail-Safe disengagement. - Signal Gap Cycles
This value has meaning only when Fail-Safe is engaged.
This is similar to the Signal Gap Cycles value, except that it works in reverse. While Fail-Safe is engaged, there is the potential that valid signal could be applied at some point in time. There is also the potential that spurious signals (noise) could be received, especially in RF environments like R/C.
It is not desirable for just any signal to be considered valid for the purpose of disengaging Fail-Safe, or Fail-Safe may disengage prematurely. Therefore, if a signal is detected, the Signal Gap Cycles value specifies how many subsequent invalid input cycles must be received before Fail-Safe disengages in order to prevent Fail-Safe from disengaging.
The factory default value for Signal Gap Cycles is 5; therefore, 5 input cycles with no (or invalid) input signal, out of 55 cycles (specified by Cycles to Disengagement) must occur to maintain Fail-Safe engagement.
Values written by the Write Fail-Safe Parameters take effect immediately, except under rare conditions I won't even try to explain. RC4 is a very dynamic device, so if changes do not take effect immediately, they will take effect within less than 1.2 seconds - usually way less than 1.2 seconds. Probably 99% of the time, changes will take effect immediately.
Be extremely careful with this command! Improper settings can cause RC4 to malfunction or stop working entirely. For proper Fail-Safe operation (desired operation not withstanding) the Signal Continuity Cycles value absolutely must be less than the Cycles to Engagement value. Similarly, the Signal Gap Cycles value must be less than the Cycles to Engagement value.
These values must be altered with care. If RC4 stops working properly after writing new values, use the Write Fail-Safe Parameters command to specify values that are known to work. If RC4 refuses to accept the new values, then reset RC4 by turning it off and turning it back on again. Always test new settings thoroughly before saving them to EEPROM as the default start-up values!
2.2.9 Read RC4 Status (0x0C)
The Read RC4 Status command returns information about the status of RC4 and
signal activity. Much of the information returned by this command is also obtainable
from the Read Channel Data command. Be aware that
status information retrieved here can be out of sync with signal data, since new signals
could arrive between the time the signal data is retrieved and status information is
retrieved. The Read Channel Data command returns data and
status information, together, for when synchronized data is desired.
Note that the status flags are delivered as two individual bytes and not as a single word
value. This is significant when considering Endianness, as the byte order remains
the same in Big Endian and Little Endian mode.
The Error Code, if non-zero, indicates that RC4 has
detected an error of some kind. If multiple errors occur before the error code is read, only
the first error that occurred will be reported. The error code is reset to zero whenever it is
read via the Read Channel Data or Read RC4 Status commands.
Error Codes Code Meaning 00 No error - all is well 01 Receive buffer overrun 02 USART Receiver framing error 03 USART Receiver overrun error 04 Specified command code not implemented 05 Transmit buffer overrun 06 EEPROM write operation failed 07 Docked module not present
(Available only if the docking feature is present)08 Unable to communicate with PIC2 09 EEPROM update interrupted by watchdog reset 0A EEPROM update interrupted by another warm reset 0B EEPROM update interrupted by power failure or hard reset 0C EEPROM data corruption detected 0D EEPROM data checksum error 0E Bad sense byte on brown-out reset - cold reset performed 0F EEPROM update attempted while EEPROM updates disabled
The Bit-Mapped Channel Input Enable Bits are simply a
collection of cfINPUT bits from each of the Channel
Configuration Bytes encoded into a single byte. The cfINPUT bit is a read-only bit from
the Channel Configuration Byte that indicates whether the channel input is enabled. This
information may be useful, depending on the application, and the bits are encoded into a single
byte for convenience.
Bit-Mapped Channel Input Enable Bits 7 6 5 4 3 2 1 0 Reserved Channel 4 Channel 3 Channel 2 Channel 1
- Bit 7: Reserved - This bit is not used.
- Bit 6: Reserved - This bit is not used.
- Bit 5: Reserved - This bit is not used.
- Bit 4: Reserved - This bit is not used.
- Bit 3: Channel 4
Reflects the setting of the cfINPUT bit from the channel configuration byte for Channel 4.
0 = Input signals or commanded pulse width values are ineffective.
1 = Channel is accepting input. - Bit 2: Channel 3
Reflects the setting of the cfINPUT bit from the channel configuration byte for Channel 3.
0 = Input signals or commanded pulse width values are ineffective.
1 = Channel is accepting input. - Bit 1: Channel 2
Reflects the setting of the cfINPUT bit from the channel configuration byte for Channel 2.
0 = Input signals or commanded pulse width values are ineffective.
1 = Channel is accepting input. - Bit 0: Channel 1
Reflects the setting of the cfINPUT bit from the channel configuration byte for Channel 1.
0 = Input signals or commanded pulse width values are ineffective.
1 = Channel is accepting input.
The Bit-Mapped Channel Input Detection Bits indicate
which channels received a valid input signal during the most recent input signal cycle. These bits
can be compared with the Physical Input Connections value,
which can be retrieved via the Read RC4 Configuration command, to
quickly determine if all of the physically connected inputs have received a signal.
Bit-Mapped Channel Input Detection Bits 7 6 5 4 3 2 1 0 Reserved Channel 4 Channel 3 Channel 2 Channel 1
- Bit 7: Reserved - This bit is not used.
- Bit 6: Reserved - This bit is not used.
- Bit 5: Reserved - This bit is not used.
- Bit 4: Reserved - This bit is not used.
- Bit 3: Channel 4
Indicates whether a valid pulse width was recorded for the Channel 4 input during the most recent input signal cycle.
0 = No valid signal was detected.
1 = A valid signal was detected and recorded. - Bit 2: Channel 3
Indicates whether a valid pulse width was recorded for the Channel 3 input during the most recent input signal cycle.
0 = No valid signal was detected.
1 = A valid signal was detected and recorded. - Bit 1: Channel 2
Indicates whether a valid pulse width was recorded for the Channel 2 input during the most recent input signal cycle.
0 = No valid signal was detected.
1 = A valid signal was detected and recorded. - Bit 0: Channel 1
Indicates whether a valid pulse width was recorded for the Channel 1 input during the most recent input signal cycle.
0 = No valid signal was detected.
1 = A valid signal was detected and recorded.
Status Byte #1 Bit Assignments 7 6 5 4 3 2 1 0 psDOCKED psLOCKOUT Reserved psEEWRITE psUPDATE psFAILSAFE psSIGNAL psONLINE
- Bit 7: psDOCKED
This bit is valid only if the docking feature is present.
Indicates the docked module is selected (enabled). The docked module is activated through the Enable Docked Module command. If no docked module is present, a watchdog reset will occur and the module will be deselected. However, it is possible to read this bit while it is still set before that happens. If the docked module is present, this bit will remain set until the Enable Docked Module command is used to disable it. - Bit 6: psLOCKOUT
Indicates the output signals are currently locked due to Noise Rejection functionality. This bit only gets set if Noise Rejection is enabled and the conditions are present to activate the temporary lock (see the mfLOCKOUT bit in the RC4 Mode command). psLOCKOUT is the counterpart to mfLOCKOUT. mfLOCKOUT enables Noise Rejection operation, and psLOCKOUT indicates when Noise Rejection is active. - Bit 5: Reserved - This bit is not used.
- Bit 4: psEEWRITE
Indicates an EEPROM write (save) operation is in progress. This bit gets set when an EEPROM update operation is requested via the Enable EEPROM Update and RC4 Special Function command combination, or during a factory settings restore operation invoked by hardware (button press on power-up). - Bit 3: psUPDATE
This bit is used internally to control the exchange of data between the two PIC microcontrollers on the RC4 mainboard. This bit gets set when PIC2 requests data from PIC1, or when PIC1 has new data to send to PIC2. It is likely that this bit will rarely, if ever, be set when read from the Read Channel Data or Read RC4 Status commands. - Bit 2: psFAILSAFE
Indicates current Fail-Safe status (0=disengaged, 1=engaged). Fail-Safe may become engaged either due to loss of signal, or by request. The RC4 Mode command can be used to programmatically control Fail-Safe engagement, or the Trigger Enable command can be used to enable Fail-Safe engagement control on the Trigger Input. The RC4 Mode bit, mfFAILSAFE is used to forcibly engage Fail-Safe. The psFAILSAFE status bit indicates when Fail-Safe is engaged, whether it is engaged through normal means or on demand. - Bit 1: psSIGNAL
Indicates whether a valid input signal was detected (0=no valid signal detected, 1=valid signal detected on at least one channel input). If Noise Rejection is enabled (see the mfLOCKOUT bit of RC4 Mode command), then this bit indicates that a valid signal was detected on all connected inputs. Only the inputs specified in the Physical Input Connections command are included in this indication.
A valid signal is defined as one where the measured pulse width falls between the minimum and maximum pulse width values (inclusive) established by the PWM Input Configuration command or the Write PWM Signal Configuration command. - Bit 0: psONLINE
Indicates Fail-Safe has been disengaged at least once since power-up or master reset. This information is important for applications that may be logging or tracking the output signals from RC4. A channel can be configured with the cfINITWAIT bit set, which means no output signal will be generated until Fail-Safe has disengaged at least once since power-up (or master reset). If the psONLINE status bit is clear, this means no output is being generated for any channel(s) configured for cfINITWAIT, even though an output signal value will be returned when read from the Read Channel Data command. The psONLINE bit also controls when output is turned on for channels that power-up in R/C Fixed mode.
Status Byte #2 Bit Assignments 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved psERROR psP1EEPROM psRESET psRESTART
- Bit 7: Reserved - This bit is not used.
- Bit 6: Reserved - This bit is not used.
- Bit 5: Reserved - This bit is not used.
- Bit 4: Reserved - This bit is not used.
- Bit 3: psERROR
This bit indicates that an error has occurred. Whenever an error occurs (that RC4 can detect), this bit gets set, and an appropriate error code is reported. When the error code is read, the error condition is cleared. If more than one error occurs before the error code is read, only the first detected error is recorded. - Bit 2: psP1EEPROM
This bit is an indication that an EEPROM save or restore operation (communication cycle) between PIC1 and PIC2 is currently pending. Immediately following power-up or reset, this can be an indication that PIC1 has not been initialized, yet. PIC1 configuration settings are stored in the EEPROM of PIC2 and thus must retrieve them from PIC2 before its fully operational state can be known. This bit can also be an indication that an EEPROM save operation has been requested and has not yet completed. This can occur most prominently when a docked module is activated and an RC4 Special Function command is issued to save PIC1 settings. The save will remain pending until the docked module is de-selected. If an update (write) operation has been requested, the psEEWRITE status bit also will be set.
- Bit 1: psRESET
This bit is similar to psRESTART, except that it indicates that a reset other than a watchdog reset has occurred in either PIC1 or PIC2. Such resets include brown-out reset, master clear reset and software reset.
The PIC1 and PIC2 Reset counts are available through the Read RC4 Status command. These values indicate how many resets have occurred since the last status read. These value get reset to zero when read.
- Bit 0: psRESTART
Indicates a watchdog reset has occurred in PIC1 or PIC2. A watchdog reset can occur in PIC1 only if there is a communication problem between PIC1 and PIC2 on the RC4 mainboard. This is either an indication of a critical hardware failure, or the absence of a docked FailSafe module following an attempted activation via the Enable Docked Module command.
There are currently no known conditions that cause a watchdog reset in PIC2. However, PIC2 is designed to resume its rigorous processing schedule, unimpeded, in the event a watchdog reset does occur.
The psRESTART status flag indicates that at least one watchdog reset has occurred since the last time the Read RC4 Status command was issued. Refer to the values obtained from the Read RC4 Status command to collect the watchdog reset counts if the psRESTART status bit is set. The Read RC4 Status command clears the reset counters to zero and clears the psRESTART status bit, so a subsequent read will return zero unless a reset occurs in the interim.
PIC2 is one of the two microcontroller chips on the RC4 main board - the one that is responsible for all the PWM signal processing. A watchdog reset can only occur in PIC2 if the docking feature is available since the watchdog timer is not used in PIC2 when the docking feature is absent. Use the Read RC4 Configuration command to retreieve the "Features" bytes to determine what features are available. The availability of the docking feature will be indicated in the PIC1 Features byte (yes, the PIC1 features byte - if it's not in PIC1, it's not in PIC2, either).
The PIC2 Warm Resets value indicates how many times the "PIC2" microcontroller has been reset due to a software reset. A software reset can occur as the result of an RC4 Special Function command, either as a result of an EEPROM operation, or as a direct software reset request. A software reset also can occur as the result of a brown-out detection (where the power supply voltage drops to a point where functionality can become unreliable).
The PIC1 Watchdog Timeouts value indicates how many times the "PIC1" microcontroller has reset due to watchdog timer time-outs (for a brief description of what a watchdog timer is, see PIC2 Watchdog Timeouts). PIC1 is one of the two microcontroller chips on the RC4 main board - the one that is responsible for all the communications between the two PICs and the serial interface. A watchdog reset indicates that something abnormal has occurred during processing, usually regarding loss of communication between the two PICs microcontrollers - something that should never happen.
A PIC1 watchdog reset can occur duing a Factory Restore process whereby the hardware method is used to restore settings. To restore factory default settings, a button connected to the proper input must be pressed down before turning on power to RC4, and held down for a few seconds after the power comes on. During this time, communication between the two PICs is disrupted, so PIC1 may reset itself once or twice before the process completes (a lapse of approx. 2.7 seconds is required for a PIC1 watchdog reset to occur).
The PIC1 Warm Resets value indicates how many times the "PIC1" microcontroller has been reset due to a software reset. A software reset can occur as the result of an RC4 Special Function command, either as a result of an EEPROM operation, or as a direct software reset request. A software reset also can occur as the result of a brown-out detection (where the power supply voltage drops to a point where functionality can become unreliable).
2.2.10 Read RC4 Configuration (0x0D)
| 0D: Read RC4 Configuration | |
|---|---|
| Value | Bytes |
| RC4 Mode Settings RC4 Interface Configuration PWM Input Configuration Physical Input Connections Trigger Enable PIC1 Features PIC2 Features |
1 1 1 1 1 1 |
The PIC1 Features byte, also available in the extended ID block in the RoboBRiX ID block, is encoded to reveal what features are implemented into the current firmware version. The byte is encoded as follows:
PIC1 Features RC4
Version7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved fp1DEBUG fp1DOCKING fp1MCLR F 1 0 0 0 0 0 0 1
- Bit 7: Reserved - This bit is reserved for factory use, only.
- Bit 6: Reserved - This bit is not defined.
- Bit 5: Reserved - This bit is not defined.
- Bit 4: Reserved - This bit is not defined.
- Bit 3: Reserved - This bit is not defined.
- Bit 2: fp1DEBUG
This bit is used only in development and indicates whether debug commands are available. Debug options are not available in publicly released versions of the firmware. - Bit 1: fp1DOCKING
This bit indicates if docking functionality is included. A separate FailSafe module was under development that could be docked to the RC4 main board for programming. Development of this module was discontinued, so docking functionality was removed from RC4. However, the docking feature remains a viable option for any future modules that may take advantage of it. - Bit 0: fp1MCLR
If this bit indicates if the hardware master reset functionality is included. Master reset functionality was implemented beginning with Revision F of RC4.
PIC2 Features RC4 Version 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved fp2MIXED fp2EEPROM fp2FAILSAFE F 0 0 0 0 0 1 1 0
- Bit 7: Reserved - This bit is not defined.
- Bit 6: Reserved - This bit is not defined.
- Bit 5: Reserved - This bit is not defined.
- Bit 4: Reserved - This bit is not defined.
- Bit 3: Reserved - This bit is not defined.
- Bit 2: fp2MIXED
This bit indicates that PIC2 supports unsequenced input connections. This means that channels 1 through 4 do not need to be connected to an input source in the same order as the signals are demultiplexed. However, there remains the restriction that all four input signals must be adjacent to each other in the demultiplexed group, and only one channel input should receive an active signal at any given time (although, under certain [restrictive] conditions, PIC2 can [accurately] sample multiple simultaneous input signals). - Bit 1: fp2EEPROM
This bit indicates EEPROM save & restore functionality is included. This became available with Revision F of RC4, and includes the ability to save and restore PIC1 configuration options. - Bit 0: fp2FAILSAFE
This bit is set only for stand-alone FailSafe modules. A FailSafe module uses much of the same firmware code as PIC2 of the RC4 mainboard, but with slightly different default configuration values and behavior. This bit is always clear for PIC2 on the RC4 mainboard, but will always be set when examining the PIC of a docked FailSafe module. The stand-alone FailSafe module firmware is still under analysis and in development.
UPDATE: Development of the FailSafe module has been discontinued. This feature is no longer valid.
2.2.11 Read Trigger Input (0x0E)
| 0E: Read Trigger Input | |
|---|---|
| Value | Bytes |
| Trigger Input Pulse Width | |
The Trigger Input is used to trigger events based on the pulse width of a signal, or signals, received on this input. Currently, there is only one, fixed, threshold setting that is used to control event triggering. This threshold is set to 4500 (or 0x1194 in hexadecimal), which equates to a 1.5ms pulse width. Any pulse width shorter than that envokes any events that are enabled, and any pulse width longer than that terminates or cancels any events or event states that may be in effect.
Currently, there is only one built-in event that can be enabled on the Trigger Input, and that is to force-activate the Fail-Safe state (otherwise known as "Fail-Safe on Demand"). For more information on Fail-Safe on Demand (or FSOD), see the RC4 Mode command. For more information about activating trigger events, see the Trigger Enable command.
If the FSOD function is enabled on the Trigger Input, then the Read Trigger Input command will return zero whenever there is no input signal present. Otherwise, the command will return the value of the last signal received.
The two-byte value returned is affected by the Endianness setting (see RC4 Interface Configuration for more information about Endianness).
2.2.12 Read Next Byte (0x0F)
| 0F: Read Next Byte | |
|---|---|
| Value | Bytes |
| Next Byte from RC4 Transmit Buffer | |
In byte mode, RC4 stores return data in its own internal (16-byte) buffer and will return exactly one byte in response to any command that returns data. If more than one byte of data is expected in response to a command, then issuing the Read Next Byte command will retrieve the next byte of data in the stream. This allows a slow host to retrieve a data stream one byte at a time at whatever rate it needs.
The number of data bytes returned by any given command is always known, so the host should always know how many bytes to expect and should call Read Next Byte only as many times as is necessary to collect all the data bytes. Read Next Byte will return zero if there is no more data available to return.
If another command is issued before all data bytes are read, the internal buffer will be cleared and replaced with any data that is expected from the new command. In other words, any data returned by the new command overwrites whatever is in the buffer, and any unread data from a previous command is lost.
The Read Next Byte command only functions when RC4 is configured for byte mode and will always return zero if used in burst mode. Burst mode or byte mode is established using the RC4 Interface Configuration special command.
Data returned by Read Next Byte is returned in the order determined by the Endianness setting (again, see RC4 Interface Configuration). This applies to any two-byte value(s) that may appear in the returned data.
2.3 RC4 Special Commands
The following commands are "special" commands that either define operating parameters for RC4 in general, or invoke seldom-used operations (such as saving settings to EEPROM).
RC4 Special Commands Command Hex Bit Number Send/Receive Description 7 6 5 4 3 2 1 0 Special Function E0 1 1 1 0 0 0 0 0 Send Execute a Special Function f f f f f f f f Send First 8-bit data byte ffffffff of function code E0 1 1 1 0 0 0 0 0 Send Special Function Command again s s s s s s s s Send Second 8-bit data byte ssssssss of function code RC4 Mode E1 1 1 1 0 0 0 0 1 Send Set RC4 Operating Mode. x r x l e s b f Send Mode Selection Byte RC4 Interface E2 1 1 1 0 0 0 1 0 Send RC4 Command Interface Configuration x e d d m b b b Send Define command interface operating parameters PWM Configuration E3 1 1 1 0 0 0 1 1 Send Select PWM Configuration x x x x x i i i Send Configuration Index (0-7) Input Connections E4 1 1 1 0 0 1 0 0 Send Specify Channel Input Connections x x x x 4 3 2 1 Send Enables physical channel input connections Trigger Enable E5 1 1 1 0 0 1 0 1 Send Select PWM Configuration x x x x x x x i Send Trigger Enable Bits Enable EEPROM E6 1 1 1 0 0 1 1 0 Send Enable EEPROM Updates A5 1 0 1 0 0 1 0 1 Send Allows EEPROM update functions to work Docked Module E7 1 1 1 0 0 1 1 1 Send Enable docked FailSafe module d d d d d d d d Send Selects docked module for access (0=undock)
2.3.1 RC4 Special Function (0xE0)
The RC4 Special Function command is used to invoke infrequently-used features
of RC4, mostly for EEPROM save and restore operations.
All RC4 Special Function codes are two bytes long. However, only one byte of a
two-byte code can be specified at a time. Therefore, to invoke a special function, the
RC4 Special Function command must be executed twice - once to write the first byte of the
function code, and again to write the second byte of the function code. The function is executed
immediately following the write of the second byte. This is done primariy to protect against
accidental executions of special functions.
Only specific Special Function code sequences will evoke actions. A zero data byte
is considered invalid and serves to cancel or clear any current or
incomplete Special Function command sequence. It is good practice to
execute the Special Function command twice with a zero byte before
executing a valid Special Function command sequence.
For example: E0 00 E0 00, referred to as Special Function code 00 00.
NOTE: Before issuing a Special Function command to save settings to
the EEPROM, the Enable EEPROM command must be
issued, first, or the Special Function command will generate an error.
Also, be aware that if the mfRESETCMD bit is set via the RC4 Modes
command, any incomplete Special Function command sequence is automatically cleared
if more than 5 seconds elapses between the first and second calls to supply the function code.
Special Function Codes Data Bytes Special Function First Second 00 00 Enter normal operating mode (and/or clear E0 expectations) EE 01 Save current channel values to Fail-Safe EEPROM EE 02 Save RC4 PIC2 settings to EEPROM EE 04 Save RC4 PIC1 settings to EEPROM EE 7F Save all RC4 settings to EEPROM FA 7F Restore all settings to factory defaults FA 80 Recall default factory settings without EEPROM update FF FF Perform software reset Example: To save RC4 settings to EEPROM, the Special Function command must be performed twice by writing the following four bytes: E0 EE E0 02
The code sequences presented above are described in more detail, below:
- EE 01
- Saves the current channel values to EEPROM. Depending on the setting of the mfIOEEPROM bit (see RC4 Modes), the values that are saved are either provided by host, or are captured from the channel outputs. If mfIOEEPROM is set, then the values are taken from the last Write Channel Data command. Otherwise, if mfIOEEPROM is clear, then whatever signal values are driving the channel outputs are saved to EEPROM. This establishes the current settings as "presets" for output signal values for channels that are configured for R/C Fixed mode.
- EE 02
- Saves the current RC4 PIC2 settings to EEPROM, which includes the following:
- PWM Input Configuration (1 byte)
- PWM Signal Configuration (4 bytes)
- Fail-Safe Operating Parameters (4 bytes)
- Physical Input Connections (1 byte)
- RC4 Mode (1 byte - only bits pertaining to PIC2 are observed)
- RC4 Status Byte #1 (1 byte - for the psFAILSAFE bit, only)
- Channel Configuration Bytes for Channels 1-4 (4 bytes)
- EE 04
- Saves the current RC4 PIC1 settings to EEPROM, which includes the following:
- RC4 Mode (1 byte - only bits pertaining to PIC1 are observed)
- RC4 Interface Configuration (1 byte)
- Trigger Enable (1 byte)
- EE 7F
- Saves all RC4 configuration data (from PIC1 & PIC2) to EEPROM. Essentially combines the EE 01, EE 02 and EE 04 Special Mode command byte sequences.
- FA 7F
- Restores all EEPROM values to initial factory default settings. Followed by software reset. The Factory Restore operation is not selective. In other words, one cannot selectively restore settings or channel presets, etc. All settings are restored to factory defaults.
- FA 80
- Configures RC4 with factory default settings (with the exception of serial interface settings). The main difference between this command and FA 7F is that this command does not save factory default settings back to the EEPROM (i.e. the factory default settings are not permanently restored).
- FF FF
- Performs RC4 software reset, restoring RC4 to its power-up configuration.
2.3.2 RC4 Mode (0xE1)
The RC4 Mode command is used to establish various operating modes that apply to RC4 in general, independent from the various operating modes that can be applied to individual channels. RC4 Mode settings that affect the channels will affect all channels.
The RC4 Mode command must be followed by one data byte. This data byte uses a bit-mapped encoding scheme for specifying the desired modes. In other words, each bit of the byte serves to enable or disable a particular feature.
The RC4 Mode bit settings are encoded as follows:
RC4 Mode Bit Assignments RC4 Defaults 7 6 5 4 3 2 1 0 Reserved mfRESETCMD Reserved mfLOCKOUT mfIOEEPROM mfIOTABLE mfFSODNOW mfFAILSAFE F 0 0 0 0 0 1 0 0
- Bit 7: Reserved - This bit is not used
- Bit 6: mfRESETCMD -- Incomplete-Command Automatic Reset.
1 = Enabled, 0 = Disabled (default)
Most RC4 commands require more than one byte to be written for the command to be complete. If an incomplete command has accumulated in the internal receive buffer, any subsequent commands will arrive out of sync and can cause problems or produce unexpected results. mfRESETCMD provides a means of automatically clearing incomplete commands from the internal command buffer. When this bit is set, if a partial command sequence is issued, it will be automatically cleared after a delay of approximately 5 seconds. This reset only occurs if a partial command byte sequence has accumulated in the internal receive buffer. Note that when this reset occurs, it also automatically clears out any incomplete RC4 Special Function command sequence. If mfRESETCMD is cleared, this automatic reset function is disabled, and the reset will not occur. - Bit 5: Reserved - This bit is not used
- Bit 4: mfLOCKOUT -- Noise Rejection Enable
1 = Enabled, 0 = Disabled (default).
Setting this bit enables Noise Rejection operation. This means that for channels that are configured to respond to R/C signals (any R/C mode, plus Command Override and Command Protected modes), between the time signal is lost (even if only for one frame) and the time Fail-Safe engages, the channel outputs are locked in at the last good signal that was present before the loss of signal. A period of good signal lasting a shorter period of time than is normally required to disengage Fail-Safe, will cause the outputs to once again respond to inputs. During this period, however, the outputs will not respond to any input signal - good or bad. This feature helps improve response stability in situations where signal may be weak. Another side- effect of setting this bit is that all active inputs must have a valid signal, or the entire input cycle will be rejected. - Bit 3: mfIOEEPROM -- EEPROM Channel Presets Source Selection
1 = Commanded values from host, 0 = Output signals (default).
The function of this bit is similar to that of mfIOTABLE, but operates independently and affects RC4 Special Function commands that save signal data to EEPROM. This data is used in establishing channel "presets" for the R/C Presets mode of operation (to drive the outputs with known signals when Fail-Safe is engaged), and for channels that power up in R/C Fixed mode. The mfIOEEPROM bit selects which data gets saved to EEPROM - either the signal values provided by the host, or the values used to generate the PWM output signals.
- Bit 2: mfIOTABLE -- Channel Data Sample Source
1 = Input signals (default), 0 = Output signals.
One of the primary features of RC4 is its ability to sample PWM inputs, essentially converting pulse widths to numeric values. However, the channels may be configured to get their input from other sources (from the host, from EEPROM, or from a static internal sample buffer in the case of cfPASSTHRU mode). Therefore, the signal that is on the channel output may be following an input source other than the PWM inputs. When a command is issued to read channel data, the values sampled from the PWM inputs are returned by default. However, depending on the application, it may be desirable to record the output signals, instead. The mfIOTABLE bit is used to select which data set is provided. When this bit is set, the pulse width values sampled from the PWM inputs are returned. When this bit is clear, the pulse width values used to generate the output signals are returned.
Note that this mode applies to all channels and is exclusive. Only input data or output data can be obtained from a signal, not both, and it is not possible to configure one channel to return input data and another to return output data. - Bit 1: mfFSODNOW -- Fail-Safe-On-Demand (FSOD) Activation Behavior
1 = Immediate, 0 = Delayed (default)
This bit augments the behavior of Fail-Safe engagement and is effective only at the time bit 0, mfFAILSAFE, gets set. If mfFSODNOW is set, Fail-Safe mode will engage the moment FSOD is requested (mfFAILSAFE is set). If mfFSODNOW is clear, then when FSOD is requested, RC4 will behave as though the input signal is lost, and Fail-Safe will engage only after the Fail-Safe mechanism has determined that input signal is absent. Note, however, that this does not affect the reporting of the psSIGNAL bit in RC4 Status Byte #1. Although RC4 will behave as if no signal is present, the status bit will still report whether or not a valid signal is actually present. - Bit 0: mfFAILSAFE -- Fail-Safe-On-Demand (FSOD)
1 = Demand Fail-Safe mode, 0 = Normal mode (default).
This bit provides a means of overriding the normal Fail-Safe activation mechanism to forcibly engage Fail-Safe mode upon request. Setting this bit forces Fail-Safe to engage regardless of whether any input signal is present.
Note that although Fail-Safe can be forcibly engaged by setting mfFAILSAFE, it cannot be forcibly disengaged by clearing the bit. Clearing mfFAILSAFE only re-enables normal Fail-Safe functionality, and only the reception of a good input signal can subsequently disengage Fail-Safe.
The setting and clearing of the mfFAILSAFE bit is controlled either by the RC4 Mode command, or by Trigger Enable, but not both. If FSOD control is enabled on the Trigger Input, then mfFAILSAFE cannot be affected by the RC4 Mode command. The mfFAILSAFE bit can be affected by the RC4 Mode command only when FSOD is not enabled on the Trigger Input.
When mfFAILSAFE is set, its immediate behavior is further augmented by the setting of bit 1, mfFSODNOW.
The Read RC4 Status command can be used to determine if Fail-Safe is currently engaged.
RC4 Mode Byte Summary Bit Meaning 7 Reserved Ignored - not implemented 6 mfRESETCMD Reset incomplete RC4 commands
0 = Incomplete command reset is disabled
1 = Incomplete command reset is enabled5 Reserved Ignored - not implemented 4 mfLOCKOUT Noise Rejection
0 = Noise Rejection disabled
1 = Noise Rejection enabled3 mfIOEEPROM I/O selection for EEPROM saves
0 = Output signal values are saved
1 = Commanded signal values are saved2 mfIOTABLE I/O selection for channel sampling
0 = Output signal values are read
1 = Input signal values are read1 mfFSODNOW Behavior of Fail-Safe-on-Demand
0 = Fail-safe engages immediately
1 = Fail-safe engages after a delay0 mfFAILSAFE Fail-Safe-on-Demand (FSOD)
0 = Normal RC4 operation
1 = Forcibly activate Fail-Safe
2.3.3 RC4 Interface Configuration (0xE2)
The RC4 Interface Configuration command is used to establish the settings required for communication over the serial interface. Note that in order to issue this command, the host must be able to talk to RC4 at whatever speed it is currently set to (factory setting is 2400 bps). Also, if the speed setting is altered by this command, the host will need to reconfigure the speed of its serial port to match in order to regain communication with RC4. RC4 does not have an auto-detect speed feature!
The RC4 Interface Configuration command requires only one data byte. The bits
of this byte are encoded to specify Endianness, Extended Data Level, Data Mode and Bit
Rate selections (see table, below). Note that if only one of these options needs to be changed,
the others must be preserved. Therefore, the host should maintain a copy of this byte so
that when one or more selections need to be altered, only the bits of interest should be
modified and then the new byte written to RC4 by issuing this command again.
The RC4 Interface Configuration byte is encoded as follows:
RC4 Interface Configuration Byte 7 6 5 4 3 2 1 0 Reserved Endianness
0=Little
1=BigExtended Data
00=Base Data Only
01=Level 1 Extended
10=Level 2 Extended
11=Level 3 ExtendedData Mode
0=Burst
1=ByteBit Rate
000=1200 bps
001=2400 bps*
010=4800 bps
011=9600 bps
100=19200 bps
101=38400 bps
110=56000 bps
111=57600 bps
Endianness refers to the order in which data bytes are returned, and it applies only to values that are larger than one byte. Some RC4 commands return two-byte values, such as those that return channel input pulse width values. The order in which the bytes of these values is returned is determined by the Endianness setting.
In Big Endian mode, the high byte is transmitted first, followed by the low byte. In Little Endian mode, the low byte is transmitted first, followed by the high byte. This is useful for accommodating a variety of host processors. For example, computers running Windows operating systems operate in Little Endian mode, whereas a MIPS embedded processor may operate in Big Endian mode.
It is important to remember that if a command returns a stream of data (such as the Read Channel Data command configured to return extended data), the order of the values returned is not affected. Only the byte order of any two-byte values within the data stream affected. Therefore, Read Channel Data will always return Channel 1, Channel 2, Channel 3 and Channel 4 values in the same sequence, but the byte order would be high,low,high,low,high,low,high,low in Big Endian mode, or low,high,low,high,low,high,low,high, in Little Endian mode.
Extended Data bits are used to specify what data is returned by the Read Channel Data command.
Since there are separate read commands to retrieve sampled signal data from the channels and status information about the channels, it is possible that the status information could be out of sync with the data, since an update could occur between the two reads. Therefore, a mechanism has been provided to return synchronized data and status information in response to a single command. The Extended Data bits are used to select the data that is returned by the Read Channel Data command.
When these bits are zero, only the signal data is returned for the four input channels (this is the default setting). There are three additional levels of information that can be selected (see the Read Channel Data command for more information).
Note that these bits only need to be set once to affect all subsequent channel data reads. These bits can be changed at any time to change the data reporting level.
Data Mode determines how data is returned by all RC4 commands that return data. If this bit is zero, then this is considered "Burst" mode, and all data in response to a read command is transmitted in a continuous stream at whatever the current bit rate setting is. This is fine for hosts that either collect the data into a buffer or that run fast enough to process each byte as it is returned.
When the Data Mode bit is set, this puts RC4 in "Byte" mode. In this mode, all data that is returned by a read command is kept in a buffer inside RC4 and is delivered one byte at a time. The first byte is returned immediately after issuing the read command. Any and all subsequent bytes are retrieved by successive Read Next Byte commands. This allows a slower host to process the data at whatever speed it can handle.
Burst mode is the default mode of operation.
Bit Rate bits select the speed at which the serial interface operates. The default factory setting sets these bits to 001 to select 2400 bps, which is compatible with RoboBRiX. The table above lists the possible settings for these bits and their corresponding bit rates.
All data transmitted (and received) by RC4 across the serial interface is structured as 8 data bits, one start bit, one stop bit and no parity. Since there is no parity checking, there is no way that RC4 can determine if the data it receives is valid. Whereas RC4 can detect framing errors or overrun errors, it is unable to detect errors that may creep into the data. However, an actual data error is such a highly unlikely event in anything but the most extreme environments, it is of little concern. Nevertheless, the following table is provided to indicate the potential error rates of the various bit rate settings.
| Bit Rate | Error Rate |
|---|---|
| 1200 | 0.16% |
| 2400 | 1.46% |
| 4800 | 0.16% |
| 9600 | 0.16% |
| 19200 | 0.16% |
| 38400 | 2.8% |
| 56000 | 3.02% |
| 57600 | 0.16% |
2.3.4 PWM Input Configuration (0xE3)
The following table lists the values assigned to MSINPUT, MSOUTPUT, FSTIMEOUT and FSRELEASE when a particular index number is specified. Also listed are the values that are assigned to the PWM MIN and MAX settings following a PWM Input Configuration command. MIN and MAX values can be altered through the Write PWM Signal Configuration command. If you are not familiar with these parameters and how they affect RC4 operation, then this table will be of little use. What is important to note is the "Period" value. Every R/C receiver repeats its signal cycle on a periodic basis - somewhere around 20ms. The correct PWMIDX setting for your receiver is the index that is closest to the signal period of your receiver. For example, if your receiver's signal cycle repeats every 20ms (50.0 Hz), then set PWMIDX to 4.
| Index | Period | Pulse Min | Pulse Max | MSINPUT | MSOUTPUT | FSTIMEOUT | FSRELEASE | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ms | Hz | MIN | us | Duty | MAX | us | Duty | ||||||
| 18.0 | 55.56 | 0A8C | 938.7 | 5.2% | 1900 | 2133.3 | 11.85% | 9688 | 2158 | 19ms | 35 | 37 | |
| 18.5 | 54.05 | 0A8C | 938.7 | 5.1% | 19BB | 2195.7 | 11.87% | 939A | 1B7C | 19.5ms | 33 | 36 | |
| 19.0 | 52.63 | 0A8C | 938.7 | 4.9% | 1A77 | 2258.3 | 11.89% | 90AC | 15A0 | 20ms | 32 | 35 | |
| 19.5 | 51.28 | 0A8C | 938.7 | 4.8% | 1B32 | 2320.7 | 11.90% | 8DBE | 0FC4 | 20.5ms | 31 | 33 | |
| 20.0 | 50.00 | 0A8C | 938.7 | 4.7% | 1BEE | 2383.3 | 11.92% | 8AD0 | 09E8 | 21ms | 30 | 32 | |
| 20.5 | 48.78 | 0A8C | 938.7 | 4.6% | 1CA9 | 2445.7 | 11.93% | 87E2 | 040C | 21.5ms | 2E | 31 | |
| 21.0 | 47.62 | 0A8C | 938.7 | 4.5% | 1D65 | 2508.3 | 11.94% | 84F4 | 0000 | 21.8ms+ | 2E | 30 | |
| 21.5 | 46.51 | 0A8C | 938.7 | 4.4% | 1E20 | 2570.7 | 11.96% | 8206 | 0000 | 21.8ms+ | 2E | 2E | |
The FSTIMEOUT value specifies how many signal cycles must be absent before Fail-Safe mode engages. The FSRELEASE value specifies how many signal cycles must be valid before Fail-Safe mode disengages. The values listed in the table are computed for approximately one second in each case. After specifying a PWMIDX values, the Write Fail-Safe Configuration command can be used to modify these values, although this is not recommended.
Note that the FSREJECT0 and FSREJECT1 values are not listed in this table. If you are not familiar with what these values are and how they affect RC4 operation, then the use of the Write Fail-Safe Configuration command is HIGHLY discouraged!
E3 requires one data byte to specify the PWMIDX value. For example:
E3 04 ; Sets RC4 for a 20ms input signal period
2.3.5 Physical Input Connections (0xE4)
E4 requires one data byte to specify input connections. This byte is bit-mapped such that bit 0 refers to channel 1, and bit 3 refers to channel 4. A zero bit indicates that a channel input is not connected, and a one bit indicates that it is connected.
For example:
E4 07 ; Indicates channels 1, 2 & 3 are connected, but channel 4 is not
If a channel is configured as disconnected, any signal that may be physically connected to that input will be ignored. Therefore, a software disconnect is as effective as a hardware disconnect.
It is important to remember that if a channel input is configured as connected, and no physical connection is present, RC4 will not function. RC4 will produce output signals, but no new signals will get through, because it is unable to detect a complete signal set. If one connected input lacks signal, any and all signals present on the remaining inputs are discarded.
2.3.6 Trigger Enable (0xE5)
Since the Trigger Input signal value can be read by the host, the host is free to implement whatever triggering options it desires, externally. Therefore, there is little need for RC4 to carry the extra features that were possibly anticipated by its creator.
The Trigger Enable command accepts one byte of data to select its function. The value of this byte can be either 0 (no function assignment, which is the default) or 1 (Fail-Safe On Demand). All other values will be ignored, leaving the current selection unchanged.
The Fail-Safe On Demand feature is described in more detail in the RC4 Mode description and in various other text within this document.
Two important things to note are:
- Enabling FSOD control on the Trigger Input prevents FSOD from being controlled through software via the RC4 Mode command (i.e. FSOD is either under Trigger Input control, or it is under RC4 Mode control).
- Reading Trigger Input data will return zero while FSOD is enabled on the Trigger Input and no input signal is present.
2.3.7 Enable EEPROM Updates (0xE6)
Therefore, before issuing an RC4 Special Function command to write data to the EEPROM, the Enable EEPROM Updates command must be issued, first. The Enable EEPROM Updates command byte must be followed by a byte having the hexadecimal value of 0xA5 in order to enable EEPROM updates within RC4. The very next command must be an RC4 Special Function command for an EEPROM write to actually occur. EEPROM updates are then immediately disabled once again.
The Enable EEPROM Updates command must be given immediately prior to any and all EEPROM write operations. Additionally, if a command issued after the Enable EEPROM Updates command does not perform an EEPROM write, EEPROM updates will once again become disabled and any subsequent RC4 Special Function command will fail to update the EEPROM.
If an attempt is made to write to the EEPROM when EEPROM updates are not enabled, an error will be generated (error code 6: EEPROM write operation failed).
2.3.8 Enable Docked Module (0xE7)
This feature is not useful without a module to dock, and will cause a PIC1 watchdog reset if an attempt is made to enable an absent module.
2.4 RoboBRiX Interrupt Commands
2.5 RoboBRiX Shared Commands
Shared RoboBRiX Commands Command Hex Bit Number Send/Receive Description 7 6 5 4 3 2 1 0 Glitch FF 1 1 1 1 1 1 1 1 Send Increment Glitch Counter Glitch Read FE 1 1 1 1 1 1 1 0 Send Returns 8-bit gggggggg Glitch Counter value g g g g g g g g Receive ID Reset FD 1 1 1 1 1 1 0 1 Send Reset ID Block index ID Next FC 1 1 1 1 1 1 0 0 Send Returns the next byte from the ID block i i i i i i i i Receive Clock Pulse FB 1 1 1 1 1 0 1 1 Send Returns zero - clock feature not implemented 0 0 0 0 0 0 0 0 Receive Clock Read FA 1 1 1 1 1 0 1 0 Send Returns zero - clock feature not implemented 0 0 0 0 0 0 0 0 Receive Clock Increment F9 1 1 1 1 1 0 0 1 Send No effect - clock feature not implemented Clock Decrement F8 1 1 1 1 1 0 0 0 Send No effect - clock feature not implemented
RC4 RoboBRiX Identification Bytes Offset Name Description RC4 Value 0 RBMajor ID Block Major Version Number 1 1 RBMinor ID Block Minor Version Number 0 2 BrickID BrickID 30 3 BrickRev Brick Revision (0=A, 1=B, etc.) 6 4 BrickFlags Brick-Specific Flags 4 5 Reserved0 (use 0) Reserved for future use 0 6 Reserved1 (use 0) Reserved for future use 0 7 Reserved2 (use 0) Reserved for future use 0 8-23 UID0-15 128-bit Unique Identifier (Randomly Generated) Random 24 NameLength RoboBRiX Name Length 3 25-27 BrickName Name of RoboBRiX in ASCII "RC4" 28 VendorLength Vendor Name Length 13 29-41 VendorName Vendor Name in ASCII "CodeSmart.com" 42 OptionsLength Size of extended ID block 6 43 MajorVer1 Firmware major version # for PIC1 2 44 MinorVer1 Firmware minor version # for PIC1 2 45 Features1 Features Code for PIC1 Varies 46 MajorVer2 Firmware major version # for PIC2 2 47 MinorVer2 Firmware minor version # for PIC2 2 48 Features2 Features code for PIC2 Varies
3. Hardware
The hardware consists of a circuit schematic and a printed circuit board.
3.1 Circuit Schematic
The RC4 schematic is available here:![]()
rc4f.schRC4 was designed using the ExpressPCB tools. You will need the ExpressPCB tools to open this file. These tools are available free from www.expresspcb.com.
3.2 Printed Circuit Board
The RC4 printed circuit board layout is available here:
rc4f.pcb
RC4 was designed using the ExpressPCB tools. You will need the ExpressPCB tools to open this file. These tools are available free from www.expresspcb.com.
3.3 Parts List
The parts list for RC4 is not yet available.
4. Firmware
The firmware source code for the PIC microcontrollers at the core of RC4 is
not available. Pre-programmed chips will be available from the author
at a later date, and they will be code-protected. Sorry!
5. Software
Software for testing and controlling RC4 is not yet available.
Here's a few screen shots of alpha software in development:
- RoboBrix Identification Screen - This feature works with all RoboBrix modules
- RC4 Configuration Interface - This is used for establishing RC4 operating characteristics
- RC4 Advanced Configuration Interface - A slightly different approach for more advanced users
- RC4 Interactive Control Interface - For monitoring and controlling RC4 I/O signals, visually
6. Issues
Current pending hardware, firmware and software issues are noted here.
6.1 Hardware Issues
- Reference 06/26/2003: Sure would be nice to have in-circuit programming capability.
- With docking functionality removed, RB0 on PIC2 is used as an LED output to indicate when the factory restore button (input) has been pressed long enough for the restore to take place. RB0 is connected to RB7 of PIC1 on the PCB. Be sure PIC1 configures RB7 as an input or consider severing this connection. PIC1 RB7 could be connected to HX5 in place of the RA0 connection there (which is also available on H2). In fact, HX4 & HX5 could be used to expose PIC1:RB7 and PIC2:RB0, respectively. Bear in mind HX connections have 10K pull-up resistors.
- Note that header H2 was moved down 0.050" in Rev G. If a shrouded header is installed, this will interfere with the mounting hole. However, where it was in Rev F, a shrouded header would interfere with the RoboBRiX header, H1.
6.2 Firmware Issues
The following firmware issues are under consideration (many of these points may not make sense to anyone but me):
High Priority Issues:
- Reference 07/29/2004: Repeat reset tests with a servo or two connected.
- Watchdog reset (in both PICs?) should check sense bytes and revert to full reset if corrupted
(or at least report an error). PIC2 does not have sense bytes implemented.
Reference 07/21/2004 for heated spew - get this implemented before I croak!
UPDATE (07/25/2004): Reset identification is unreliable. Now all resets act as POR.
UPDATE (07/30/2004): Re-instated reset paths - chip under test was deemed defective.
+ Reference 07/13/2004: This applies to brown-out reset, too! PIC2. PIC1 somehow needs to be sensitive to PIC2 resets, if not already. Figure out what mechanism is in place. - Reference 07/06/2004: No reset is observed following EEPROM save. Is this by design?
UPDATE (07/15/2004): No need to reset after save, but possbily after read.
+ Reference 07/11/2004: No (PIC1) reset is occurring after a factory restore.
Reference 07/12/2004 regarding absence of RXCONFIG cycle following restore.
Reference 06/25/2003 for PIC1 WDT reset info.
+ Reference 07/20/2004: Possibly related - EEPROM update LED blinks only after delay during save.
+ Reference 07/30/2004: What conditions cause a PIC1 WDT reset? Document them.
- Reference 07/25/2004: PIC2 reset count is not advancing after software reset.
- Reference 07/15/2004: This issue may be related to the factory restore reset problem. Make sure PIC1 only resets if docking is included and the docked module is selected. Create another mechanism to report lack of PIC2 communication.
- Reference 07/13/2004: If EEPROM sense byte indicates reset interruption, init to factory defaults in reset path (but do not perform factory restore). Limit the factory settings init to PIC2 - do not pass comm settings to PIC1. Create error code for this.
- Reference 07/13/2004: PIC2: Check for factory restore button in ALL reset paths, though be functional only in POR path. May need to identify MCLR reset to ensure factory restore is isolated to POR, only.
- Reference 07/28/2004: EEPROM corruption is occurring despite POR-only reset path.
- Reference 05/26/2004: Replace "Channel 5 Function Assignment" command with an alternate
FSOD-centric option.
Reference 07/20/2004 for more on this subject (enabling Trigger Input events).
+ Reference 07/20/2004: Implement trigger event enabling mechanism to do away with current CH5FTN. This includes bits to allow/identify FSOD control from host or trigger.
+ Reference 07/26/2004: Finish modifying Channel 5 Function (Trigger Enable) command to use bitmapped enable byte rather than a value. Add flag (somewhere?) to indicate FSOD activation source, be it Trigger Input or command (allow either to engage it). - Reference 07/23/2004: SELTABLEO is a problem again? R/C Fixed vs. R/C FailSafe.
- Reference 07/26/2004: Make Command Fail-Safe mode use presets when Fail-Safe is engaged
- Reference 07/30/2004: Make R/C Fixed mode channels power-up with values from presets in EEPROM. cfINITWAIT can be used to suspend their output until signal is present as an alternate option.
- Reference 07/16/2004: Examine the reasons why R/C Fixed mode treats signal data differently than R/C Presets mode (i.e. CTABLE vs. OTABLE). Propose arguments for revision, if any.
- Reference 07/30/2004: Consider making Read Trigger Input return a self-clearing sticky value.
- Reference 07/09/2003: Add command(s) to specify pulse width values for individual channels.
+ Reference 05/29/2003: Add a command to allow host to write data to a specified channel.
+ Consider adding commands to allow the host to selectively write position data to specific channels and/or to relatively update the position data. - Reference 07/03/2003 regarding forced Fail-Safe deactivation.
- Reference 05/22/2004: Evaluate any benefits to reporting PORTA/PORTB read values from PIC2.
- Reference 07/10/2004: Revisit NSIGNALS and LINES0 to determine what the difference is between
the two and why they both exist...and if they can be merged.
- Reference 07/15/2003 about merging NSIGNALS bits with cfINPUT bits in status byte.
+ Reference 07/15/2003: Any advantage to merging NSIGNALS bits with cfINPUT bits in status byte returns? - Reference 05/20/2004 regarding stuck Channel 5 threshold crossing LED state after config changes.
- Reference 05/20/2004: Can all servo-controller-related code be isolated to provide conditional
assembly paths to generate a controller-only version of the firmware? Perhaps a stand-alone
controller is better off as a separate project...but it would be nice to have the code.
+ Reference 07/15/2004: Yes, it would be nice to have the code. - Reference 07/20/2004: Consider adding a recovery feature to regain partial control if an input signal is physically lost while Noise Rejection is enabled.
- Reference 07/21/2004: Seems to be a problem with Trigger Input being ready too soon at power-up.
- Reference 08/13/2003: Consider adding code to stabilize Channel 5 threshold crossing detection
for FSOD. Schmitt-trigger likeness. Make thresholds programmable.
+ Implement Channel 5 triggering window, similar to a Schmitt Trigger. Perhaps add a +/- value (variable) that will define the trigger window around the current threshold.
+ Save Channel 5 threshold settings to EEPROM.
+ Add command to specify a Channel 5 threshold. Is there room for a setpoint table somewhere? - Reference 07/08/2004: 70 wait cycles were added to the end of SIGNALOUT in PIC2 to accommodate
loopback from channel 4 output to the Trigger Input. If this becomes a problem, consider
eliminating the channel 4 loopback option (jumper J8).
+ Reference 07/21/2004: Channel output connections to Trigger Input disrupt 2-wire cycle in next subsequent channel. May need to add delay prior to DELAY call (perhaps add the delay to the beginning of the DELAY routine - or have alternate entry points) before commencing with 2-wire cycles. This will take a chunk out of the 2260 cycle design limit. - Reference 07/13/2004: Consider adding a FACTORY cycle for PIC2 to tell PIC1 of button press.
- Reference 07/27/2004: It is currently impossible to establish new FSTIMEOUT/FSRELEASE, etc.
values as a result of setting PWMIDX, since the values get immediately overwritten by user
settings. Resolve this to allow pre-defined settings to prevail.
+ Reference 08/01/2004: Same issue. - Reference 08/01/2004: Convert data level value to a bitmap for Read Channel Data. This will
allow for custom data selections without having to include all data from lower groupings.
+ Reference 07/30/2004: Are the data groupings OK for the Read Channel Data command?
+ Reference 07/30/2004: Make data returns more consistent between Read Data and Read Status?
+ Reference 08/06/2004: Add another command to specify what data gets retrieved.
Low Priority Issues:
- Reference 06/24/2003: Add a verify-read pass to EEPROM update cycle(s) as well as a checksum.
Report bad checksum or bad EEPROM data if one of the two fails. Note other possible EEPROM errors
listed in journal.
Update: Verify read is in. Checksum functionality is PARTIALLY in - may be on back burner.
Update: Reference 07/05/2003: Checksum is accumulated but not written (yet) on writes.
Checksum is not yet validated (checked), either. - Reference 06/06/2003 & 06/10/2003: Add ability to add external buttons to save settings in
EEPROM (mainly for FailSafe board).
When PIC2 is not selected (via RB0 - PIC2SEL), RB1 & RB2 can be used, alternatively, as inputs. Use RB1 (DAT) - it is already used for factory restore on power-up - it can be used in the same way to envoke EEPROM saves.
UPDATE: Fail-Safe board has been discontinued.
UPDATE: It seems only saving presets would be a useful option on a button, since the only other options that can be changed requires a host connection, whereby the save can be done via a command. - Reference 06/20/2003: Add LED to PIC2 to indicate that the factory restore button has been
pressed long enough on power-up that a factory restore will happen when released.
Update: No available pins on PIC2! DEBUG pin only (and it's open-drain).
Update: Send a code to PIC1 to light up an LED there? Perhaps via PORTA/PORTB bit?
Update: With docking functionality removed, RB0 from PIC2 acts as this LED. RB0 of PIC2 remains connected to RB7 of PIC1 on the PCB, however, so this may not be a final solution. - Reference 07/13/2004: Send a byte from PIC2 to PIC1 for LED indicators - since PIC1 has pins
available and PIC2 doesn't.
UPDATE (07/25/2004): PIC1 is pretty full. Perhaps I need a rotating code display routine. Or a multiplexed output scheme. Or just go back to bed and forget about it. - Reference 07/24/2004: Consider adding a (sticky?) late-signal detection LED or status bit.
+ Reference 03/10/2003: Add an LED to indicate late signal detection.
Update: No available pins on PIC2! DEBUG pin only (and it's open-drain). - I want a [debug?] command to dump the EEPROM values.
This will require a special cycle of one form or another to send values from PIC2 to PIC1.
If this is used in troubleshooting hangs, it won't be very useful if 2-wire operation is dead. - Any desire to add bad signal detection (see 8/5/2002 entry)? Perhaps just a "bad signal" counter. This idea re-emerged (though not noted in the log) in the form of counting signal hits while failsafe is engaged. I think it would be useful.
- Implement TXFIFO overrun checking (report error, enable/disable TXFIFO processing - similar to
RXFIFO). *Is there some way a TXFIFO overrun can occur???* Yes - through bad design - if a
command attempts to transmit more than 16 bytes at a time. Therefore, TXFIFO overrun reporting
would be a DEBUG option.
Reference 06/22/2003 regarding PUTTXWORD. - Reference 06/23/2003: Any way to make PUTTXWORD work without bank switching?
- Reference 06/26/2003: Consider adding an error code buffer (FIFO) for trapping multiple errors. Or add a counter to indicate how many errors were missed.
- Reference 07/02/2003: In PIC1 WDT reset, do I want to clear any TX cycles that may be enabled in AFLAGS? Or acknowledge them by not setting RX enable bits?
- Reference 07/05/2003: Revise PIC1 reset to init reset indicators on the fly like PIC2?
UPDATE: I do not know what I meant, here! Maybe reset them after being read, like PIC2 resets them after PIC1 receives them? - Reference 07/09/2003: Consider options for expanding buffer for large "snapshots" for FOLLOWUP.
- Reference 07/24/2004: Determine current max. cycles consumed by TXPING & verify it is less than 1400 (the current worst-case limit to avoid missing an input cycle). Exclude special cycles.
- Reference 07/24/2004: Update PIC2 cycle counts for FSON, FSMODE, SELTABLEO & ISONLINE and compute best and worst case cycle times for PREOUTPUT.
- Reference 07/28/2004: Add command to allow user to override port settings to reprogram LED
outputs as inputs. And only those pins. Also save it to EEPROM as power-up setting.
May want to power-up with them as inputs and delay reconfiguration until end of reset path.
+ Reference 07/29/2004: Also add a command to allow writing to outputs as GPIO (overriding LEDs).
+ Reference 08/05/2004 for some notes regarding GPIO. - Reference 07/29/2004: Verify operation of serial interface recovery mechanism.
- Reference 07/29/2004: Any way to provide a hardware reset option to the host?
- Reference 07/30/2004: Add a self-calibration option to select PWMIDX based on input signal.
Add a self-clearing calibrate bit to PWMIDX that can be saved for auto-startup calibration?
+ Reference 07/26/2004: Add some way to specify power-up Fail-Safe state in EEPROM save.
+ Reference 07/30/2004: Add some way to specify auto-calibration state in EEPROM save.
+ It would be nice to be able to specify MIN and MAX on a per-channel basis, but this is never going to happen. Perhaps a calibration routine to determine absolute min & max?
Reference 06/25/2003 for a revisitation.
+ Add calibration mode for MIN/MAX settings.
Extremely Low Priority Issues
- Reference 03/15/2003: Regarding loss of access to TXPING. This is worth considering (consecutive WDT reset counter).
- Reference 04/26/2003: Add a Channel 5 function to switch between Mode 2 and Mode 3 R/C channel
operation/configuration.
+ Reference 07/15/2003: Consider Channel 5 functionality to switch between Mode 2 & Mode 3 R/C operation. Perhaps this is a host implementation issue? - Reference 05/26/2003: Consider my thoughts regarding continuous mode and config data selection.
- "Servo reversing" - signal inversion? It's a battle for that last cfXXX bit. cfINVERT
+ Reference 03/18/2003: Per-channel feature to disable output if input has not changed after a time. This is a battle for that last cfXXX bit. cfIDLEOFF
+ Reference 03/27/2003: See notes about mfIOTABLE (formerly smIOSAMPLE) and consider implementing a per-channel bit. Considering it, but it's a battle for the last available cfXXX bit. cfIOTABLE
+ Implement cfIOTABLE and cfIDLEOFF as optional features, controlled by assembler directive. They would be mutually-exclusive features. Another option is to implement all four competing features plus an extra [special] channel configuration byte to allow the user to specify what the bit means on a per-channel basis.
+ Reference 06/25/2003: Another contender for the last bit: cfREALTIME - to augment channels in Passthru mode so the input signal appears immediately on the output. Evaluate this.
+ Reference 07/03/2003 for another potential candidate for independent Fail-Safe operation. This, I think, is a HUGE can of worms, as it has far-reaching implications.
+ Reference 07/15/2003 regarding cfREVERT. Disregard this idea!
+ Reference 07/02/2003: Consider adding a second channel configuration byte to accommodate all proposed additions. However, code space may not allow it.
+ UPDATE (07/10/2004): The last bit was implemented as cfSIGNAL to address another problem. Any future features will REQUIRE the creation of a second configuration byte. - Reference 06/23/2003: Define how to handle software reset when FailSafe module is docked.
UPDATE: FailSafe module was discontinued, but docking remains a viable feature. - Reference 06/23/2003: Define factory restore operation when docked module is active.
- Add RC4 mode to return relative vs. absolute channel values (X vs. X - MIN).
- Make the Extended Data bits of RC4ENV apply to the Write Channel Data command as well. This
will minimize the need to execute several Special Commands in sequence for updates. Or,
perhaps, just add a Special Command to write them all at once instead of individually.
Update: Revisit this sometime. I don't think it is necessary. - Implement 8-bit sampling mode. Reference 09/02/2002, 09/15/2002 & 03/27/2003 entries. Only one bit remains in RC4ENV.
- Add a test/debug command to enable/disable all 2-wire communication between PICs.
Reference 03/05/2003 & 03/06/2003. Put on the back burner. - Retain mfTWOWIRE for future implementation? i.e. is it needed? DEBUG option?
Reference 03/27/2003 - Implement mfTWOWIRE functionality? Leave it on the back burner? - Implement EEPROM error codes...? See CMDEESTAT routine in PIC1.
Update: CMDEESTAT no longer exists! Will have to review from archives.
Reference 06/24/2003 & 06/26/2003 for more info. - Provide a Channel 5 function that will activate two pins (one active-high and one active-low) depending on programmed trigger threshold.
- Reference 03/31/2003: Any need to implement RoboBrick interrupts? Maybe if feature creep advances into the Channel 5 triggering functionality.
- Implement a PIC2 Spew command?
+ Reference 03/28/2003 - Implement PIC2 Spew functionality. Gotta figure out how. - Reference 03/19/2003: Disable Tx interrupt in PIC1 during TXPING. -- Too complex - is it worth it?
- Move MSINPUT and MSOUTPUT into Bank 0 in PIC2.
Shift variables in PIC2 so INPUTS winds up in Bank 0.
Do this if I need Aliased RAM space, otherwise only two bytes will remain available in RAM. - Add LED to indicate serial interface receive (command) buffer is empty.
- Create a converter (two 8-pin microcontrollers working together) to produce RC4-readable PWM signals from radios that produce simultaneous outputs on multiple channels.
- Reference 06/11/2004: Generate a RoboBRiX interrupt whenever an error is detected. May be more trouble than it's worth.
- Reference 06/11/2004: Consider a "dumbed-down" version of RC4. In another life.
6.3 Software Issues
No software issues listed [here], yet.
7. Documentation
Documentation for RC4 is not available at this time, but the following is planned:
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